High order delta-sigma analog-to-digital converters have a number of noise sources, offsets, etc. that deter the overall performance thereof, especially when resolving very small input voltage levels. DC offsets and gain errors have been sources of error in such ADCS, and these errors have been addressed with self-calibration systems, such as that disclosed in U.S. Pat. No. 4,943,807, issued to Early on Jul. 24, 1990. Another source of error is the non-linearity of the delta-sigma modulator, which is due in part to the feedback DAC.
The non-linearity of the feedback DAC is of more concern in a multilevel output delta-sigma modulator, as compared to a one-bit delta-sigma modulator. The one-bit modulator requires only a two-state feedback, which is inherently linear. However, the one-bit modulator does have one disadvantage in that, when the input signal is near mid-scale, large amounts of error are added to the loop during each sampling period. By utilizing a multi-level modulator, and one or more additional DAC levels, the state of the feedback DAC when the input voltage is near mid-scale is a "do nothing" state, which minimizes quantizing error RMS voltage. Such a DAC topology is disclosed in J. J. Paulos, G. T. Brauns, M. B. Steer and S. H. Ardalan, "Improved Signal-To-Noise Ratio Using Tri-Level Delta-Sigma Modulation", IEEE Proceedings ISCAS, pp. 463-466, May 1987.
One disadvantage to a multi-level feedback DAC is that the multi-level feedback no longer provides the inherent linearity of two states, as was the case in a one-bit modulator. In general, the feedback DAC in a multi-level delta-sigma modulator must be linear to the full accuracy of the overall converter. Adjusting even a third feedback state to part-per-million accuracy can be difficult. Careful selection of resistors has been attempted for audio applications, as disclosed in R. W. Adams, "Design and Implementation of an Audio 18-Bit Analog-to-Digital Converter Using Oversampling Techniques", J. Audio Eng. Soc. Vol. 34, pp. 153-166, March 1986. Another technique utilizes dynamic element matching with a dithering of imprecise DAC elements to convert linearity error into noise, which has been disclosed in L. R. Carley, "A Noise-Shaping Coder Topology for 15+ Bit Converters", IEEE J. Solid-State Circuits, Vol. SC-24, pp. 267-273, April 1989.
These previous techniques suffer a number of disadvantages in that reconfigurations of analog circuit topologies and changes in digital control waveforms are generally undesirable in any self-calibrated architecture. Digital interference coupled into analog circuitry can be removed by calibration, but any differences in interference between the calibration mode and the normal operation mode result in errors not removed by calibration. Therefore, there exists a need for a calibration system that calibrates for the non-linearities in a multi-level feedback DAC prior to utilizing the traditional delta-sigma calibration procedures to eliminate overall gain and offset errors.